Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.2.1 (lin64) Build 3414424 Sun Dec 19 10:57:14 MST 2021 | Date : Tue May 17 14:50:04 2022 | Host : chenyong-ubuntu running 64-bit Ubuntu 20.04.4 LTS | Command : report_utilization -file /media/cyubuntu/MySSD/myproject/B3VDU/sdk/vivado/b3vdu/utilization_report.txt -name utilization_1 | Design : vdu_wrapper | Device : xczu4ev-sfvc784-1-i | Speed File : -1 | Design State : Routed -------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. CLB Logic 1.1 Summary of Registers by Type 2. CLB Logic Distribution 3. BLOCKRAM 4. ARITHMETIC 5. I/O 6. CLOCK 7. ADVANCED 8. CONFIGURATION 9. Primitives 10. Black Boxes 11. Instantiated Netlists 1. CLB Logic ------------ +----------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------------+-------+-------+------------+-----------+-------+ | CLB LUTs | 60328 | 0 | 0 | 87840 | 68.68 | | LUT as Logic | 53869 | 0 | 0 | 87840 | 61.33 | | LUT as Memory | 6459 | 0 | 0 | 57600 | 11.21 | | LUT as Distributed RAM | 1792 | 0 | | | | | LUT as Shift Register | 4667 | 0 | | | | | CLB Registers | 88813 | 0 | 0 | 175680 | 50.55 | | Register as Flip Flop | 88813 | 0 | 0 | 175680 | 50.55 | | Register as Latch | 0 | 0 | 0 | 175680 | 0.00 | | CARRY8 | 1471 | 0 | 0 | 14640 | 10.05 | | F7 Muxes | 1346 | 0 | 0 | 58560 | 2.30 | | F8 Muxes | 493 | 0 | 0 | 29280 | 1.68 | | F9 Muxes | 0 | 0 | 0 | 14640 | 0.00 | +----------------------------+-------+-------+------------+-----------+-------+ 1.1 Summary of Registers by Type -------------------------------- +-------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +-------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 588 | Yes | - | Set | | 1760 | Yes | - | Reset | | 1859 | Yes | Set | - | | 84606 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. CLB Logic Distribution ------------------------- +--------------------------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+-------+-------+------------+-----------+-------+ | CLB | 13448 | 0 | 0 | 14640 | 91.86 | | CLBL | 6718 | 0 | | | | | CLBM | 6730 | 0 | | | | | LUT as Logic | 53869 | 0 | 0 | 87840 | 61.33 | | using O5 output only | 1539 | | | | | | using O6 output only | 37978 | | | | | | using O5 and O6 | 14352 | | | | | | LUT as Memory | 6459 | 0 | 0 | 57600 | 11.21 | | LUT as Distributed RAM | 1792 | 0 | | | | | using O5 output only | 0 | | | | | | using O6 output only | 594 | | | | | | using O5 and O6 | 1198 | | | | | | LUT as Shift Register | 4667 | 0 | | | | | using O5 output only | 2 | | | | | | using O6 output only | 2902 | | | | | | using O5 and O6 | 1763 | | | | | | CLB Registers | 88813 | 0 | 0 | 175680 | 50.55 | | Register driven from within the CLB | 42799 | | | | | | Register driven from outside the CLB | 46014 | | | | | | LUT in front of the register is unused | 31051 | | | | | | LUT in front of the register is used | 14963 | | | | | | Unique Control Sets | 3924 | | 0 | 29280 | 13.40 | +--------------------------------------------+-------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets. 3. BLOCKRAM ----------- +-------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------+-------+-------+------------+-----------+-------+ | Block RAM Tile | 112.5 | 0 | 0 | 128 | 87.89 | | RAMB36/FIFO* | 95 | 0 | 0 | 128 | 74.22 | | RAMB36E2 only | 95 | | | | | | RAMB18 | 35 | 0 | 0 | 256 | 13.67 | | RAMB18E2 only | 35 | | | | | | URAM | 28 | 0 | 0 | 48 | 58.33 | +-------------------+-------+-------+------------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2 4. ARITHMETIC ------------- +----------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------+------+-------+------------+-----------+-------+ | DSPs | 237 | 0 | 0 | 728 | 32.55 | | DSP48E2 only | 237 | | | | | +----------------+------+-------+------------+-----------+-------+ 5. I/O ------ +------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------------+------+-------+------------+-----------+-------+ | Bonded IOB | 24 | 24 | 0 | 252 | 9.52 | | HPIOB_M | 5 | 5 | 0 | 72 | 6.94 | | INPUT | 0 | | | | | | OUTPUT | 5 | | | | | | BIDIR | 0 | | | | | | HPIOB_S | 5 | 5 | 0 | 72 | 6.94 | | INPUT | 0 | | | | | | OUTPUT | 5 | | | | | | BIDIR | 0 | | | | | | HDIOB_M | 8 | 8 | 0 | 48 | 16.67 | | INPUT | 5 | | | | | | OUTPUT | 3 | | | | | | BIDIR | 0 | | | | | | HDIOB_S | 6 | 6 | 0 | 48 | 12.50 | | INPUT | 5 | | | | | | OUTPUT | 1 | | | | | | BIDIR | 0 | | | | | | HPIOB_SNGL | 0 | 0 | 0 | 12 | 0.00 | | HPIOBDIFFINBUF | 0 | 0 | 0 | 96 | 0.00 | | HPIOBDIFFOUTBUF | 5 | 5 | 0 | 96 | 5.21 | | OBUFDS | 5 | 5 | | | | | HDIOBDIFFINBUF | 0 | 0 | 0 | 48 | 0.00 | | BITSLICE_CONTROL | 0 | 0 | 0 | 32 | 0.00 | | BITSLICE_RX_TX | 5 | 5 | 0 | 1248 | 0.40 | | OSERDES | 5 | 5 | | | | | BITSLICE_TX | 0 | 0 | 0 | 32 | 0.00 | | RIU_OR | 0 | 0 | 0 | 16 | 0.00 | +------------------+------+-------+------------+-----------+-------+ 6. CLOCK -------- +----------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------+------+-------+------------+-----------+-------+ | GLOBAL CLOCK BUFFERs | 20 | 0 | 0 | 352 | 5.68 | | BUFGCE | 14 | 0 | 0 | 112 | 12.50 | | BUFGCE_DIV | 1 | 0 | 0 | 16 | 6.25 | | BUFG_GT | 4 | 0 | 0 | 96 | 4.17 | | BUFG_PS | 1 | 0 | 0 | 96 | 1.04 | | BUFGCTRL* | 0 | 0 | 0 | 32 | 0.00 | | PLL | 0 | 0 | 0 | 8 | 0.00 | | MMCM | 3 | 0 | 0 | 4 | 75.00 | +----------------------+------+-------+------------+-----------+-------+ * Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability. 7. ADVANCED ----------- +-----------------+------+-------+------------+-----------+--------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------+------+-------+------------+-----------+--------+ | GTHE4_CHANNEL | 2 | 2 | 0 | 4 | 50.00 | | GTHE4_COMMON | 1 | 0 | 0 | 1 | 100.00 | | OBUFDS_GTE4 | 0 | 0 | 0 | 2 | 0.00 | | OBUFDS_GTE4_ADV | 0 | 0 | 0 | 2 | 0.00 | | PCIE40E4 | 0 | 0 | 0 | 2 | 0.00 | | PS8 | 1 | 0 | 0 | 1 | 100.00 | | SYSMONE4 | 0 | 0 | 0 | 1 | 0.00 | | VCU | 1 | 0 | 0 | 1 | 100.00 | +-----------------+------+-------+------------+-----------+--------+ 8. CONFIGURATION ---------------- +-------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------+------+-------+------------+-----------+-------+ | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | DNA_PORTE2 | 0 | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | FRAME_ECCE4 | 0 | 0 | 0 | 1 | 0.00 | | ICAPE3 | 0 | 0 | 0 | 2 | 0.00 | | MASTER_JTAG | 0 | 0 | 0 | 1 | 0.00 | | STARTUPE3 | 0 | 0 | 0 | 1 | 0.00 | +-------------+------+-------+------------+-----------+-------+ 9. Primitives ------------- +---------------+-------+---------------------+ | Ref Name | Used | Functional Category | +---------------+-------+---------------------+ | FDRE | 84606 | Register | | LUT3 | 17855 | CLB | | LUT6 | 17395 | CLB | | LUT4 | 12753 | CLB | | LUT5 | 9528 | CLB | | LUT2 | 8663 | CLB | | SRL16E | 4321 | CLB | | RAMD32 | 2114 | CLB | | SRLC32E | 2109 | CLB | | LUT1 | 2027 | CLB | | FDSE | 1859 | Register | | FDCE | 1760 | Register | | CARRY8 | 1471 | CLB | | MUXF7 | 1346 | CLB | | FDPE | 588 | Register | | RAMS64E | 576 | CLB | | MUXF8 | 493 | CLB | | RAMS32 | 300 | CLB | | DSP48E2 | 237 | Arithmetic | | RAMB36E2 | 95 | BLOCKRAM | | RAMB18E2 | 35 | BLOCKRAM | | URAM288 | 28 | BLOCKRAM | | BUFGCE | 14 | Clock | | INBUF | 10 | I/O | | IBUFCTRL | 10 | Others | | OSERDESE3 | 5 | I/O | | OBUFDS | 5 | I/O | | OBUF | 4 | I/O | | BUFG_GT_SYNC | 4 | Clock | | BUFG_GT | 4 | Clock | | MMCME4_ADV | 3 | Clock | | GTHE4_CHANNEL | 2 | Advanced | | VCU | 1 | Advanced | | PS8 | 1 | Advanced | | IBUFDS_GTE4 | 1 | I/O | | GTHE4_COMMON | 1 | Advanced | | BUFG_PS | 1 | Clock | | BUFGCE_DIV | 1 | Clock | +---------------+-------+---------------------+ 10. Black Boxes --------------- +----------+------+ | Ref Name | Used | +----------+------+ 11. Instantiated Netlists ------------------------- +---------------------------------+------+ | Ref Name | Used | +---------------------------------+------+ | vdu_zynq_ultra_ps_e_0_0 | 1 | | vdu_xbar_5 | 1 | | vdu_xbar_4 | 1 | | vdu_xbar_3 | 1 | | vdu_xbar_2 | 1 | | vdu_xbar_1 | 1 | | vdu_xbar_0 | 1 | | vdu_vcu_0_0 | 1 | | vdu_v_tc_0_0 | 1 | | vdu_v_smpte_uhdsdi_rx_ss_0_1 | 1 | | vdu_v_smpte_uhdsdi_rx_ss_0_0 | 1 | | vdu_v_proc_ss_2_1 | 1 | | vdu_v_proc_ss_2_0 | 1 | | vdu_v_proc_ss_0_1 | 1 | | vdu_v_proc_ss_0_0 | 1 | | vdu_v_mix_0_0 | 1 | | vdu_v_frmbuf_wr_0_1 | 1 | | vdu_v_frmbuf_wr_0_0 | 1 | | vdu_v_frmbuf_rd_0_0 | 1 | | vdu_v_axi4s_vid_out_0_0 | 1 | | vdu_util_ds_buf_0_0 | 1 | | vdu_uhdsdi_gt_0_0 | 1 | | vdu_proc_sys_reset_2_0 | 1 | | vdu_proc_sys_reset_1_0 | 1 | | vdu_proc_sys_reset_0_0 | 1 | | vdu_lvds_7to1_0_0 | 1 | | vdu_compact_gt_ctrl_0_0 | 1 | | vdu_clk_wiz_1_0 | 1 | | vdu_clk_wiz_0_0 | 1 | | vdu_axis_subset_converter_0_0 | 1 | | vdu_axi_timer_0_1 | 1 | | vdu_axi_timer_0_0 | 1 | | vdu_axi_gpio_0_1 | 1 | | vdu_axi_gpio_0_0 | 1 | | vdu_auto_us_4 | 1 | | vdu_auto_us_3 | 1 | | vdu_auto_us_2 | 1 | | vdu_auto_us_1 | 1 | | vdu_auto_us_0 | 1 | | vdu_auto_pc_1 | 1 | | vdu_auto_pc_0 | 1 | | vdu_auto_ds_1 | 1 | | vdu_auto_ds_0 | 1 | | vdu_auto_cc_6 | 1 | | vdu_auto_cc_5 | 1 | | vdu_auto_cc_4 | 1 | | vdu_auto_cc_3 | 1 | | vdu_auto_cc_2 | 1 | | vdu_auto_cc_1 | 1 | | vdu_auto_cc_0 | 1 | | vdu_RGB2LVDS7_0_0 | 1 | | bd_ebfa_v_vid_in_axi4s_0 | 1 | | bd_ebfa_v_smpte_uhdsdi_rx_0 | 1 | | bd_ebfa_v_sdi_rx_vid_bridge_0 | 1 | | bd_d6e9_csc_0 | 1 | | bd_d689_vsc_0 | 1 | | bd_d689_smartconnect_0_0 | 1 | | bd_d689_rst_axis_0 | 1 | | bd_d689_reset_sel_axis_0 | 1 | | bd_d689_input_size_set_0 | 1 | | bd_d689_hsc_0 | 1 | | bd_d689_axis_register_slice_0_0 | 1 | | bd_d689_axis_fifo_0 | 1 | | bd_2b3b_v_vid_in_axi4s_0 | 1 | | bd_2b3b_v_smpte_uhdsdi_rx_0 | 1 | | bd_2b3b_v_sdi_rx_vid_bridge_0 | 1 | | bd_1648_vsc_0 | 1 | | bd_1648_smartconnect_0_0 | 1 | | bd_1648_rst_axis_0 | 1 | | bd_1648_reset_sel_axis_0 | 1 | | bd_1648_input_size_set_0 | 1 | | bd_1648_hsc_0 | 1 | | bd_1648_axis_register_slice_0_0 | 1 | | bd_1648_axis_fifo_0 | 1 | | bd_1628_csc_0 | 1 | +---------------------------------+------+