Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.2.1 (lin64) Build 3414424 Sun Dec 19 10:57:14 MST 2021 | Date : Fri May 6 16:43:02 2022 | Host : chenyong-ubuntu running 64-bit Ubuntu 20.04.4 LTS | Command : report_utilization -file /media/cyubuntu/MySSD/myproject/temp/b3vcu_test/utilization_report.txt -name utilization_1 | Design : arm_wrapper | Device : xczu7ev-ffvc1156-2-i | Speed File : -2 | Design State : Routed ------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. CLB Logic 1.1 Summary of Registers by Type 2. CLB Logic Distribution 3. BLOCKRAM 4. ARITHMETIC 5. I/O 6. CLOCK 7. ADVANCED 8. CONFIGURATION 9. Primitives 10. Black Boxes 11. Instantiated Netlists 1. CLB Logic ------------ +----------------------------+--------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------------+--------+-------+------------+-----------+-------+ | CLB LUTs | 138665 | 0 | 0 | 230400 | 60.18 | | LUT as Logic | 126527 | 0 | 0 | 230400 | 54.92 | | LUT as Memory | 12138 | 0 | 0 | 101760 | 11.93 | | LUT as Distributed RAM | 1240 | 0 | | | | | LUT as Shift Register | 10898 | 0 | | | | | CLB Registers | 260021 | 0 | 0 | 460800 | 56.43 | | Register as Flip Flop | 260021 | 0 | 0 | 460800 | 56.43 | | Register as Latch | 0 | 0 | 0 | 460800 | 0.00 | | CARRY8 | 2808 | 0 | 0 | 28800 | 9.75 | | F7 Muxes | 5558 | 0 | 0 | 115200 | 4.82 | | F8 Muxes | 1503 | 0 | 0 | 57600 | 2.61 | | F9 Muxes | 0 | 0 | 0 | 28800 | 0.00 | +----------------------------+--------+-------+------------+-----------+-------+ 1.1 Summary of Registers by Type -------------------------------- +--------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +--------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 476 | Yes | - | Set | | 12466 | Yes | - | Reset | | 4655 | Yes | Set | - | | 242424 | Yes | Reset | - | +--------+--------------+-------------+--------------+ 2. CLB Logic Distribution ------------------------- +--------------------------------------------+--------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+--------+-------+------------+-----------+-------+ | CLB | 28558 | 0 | 0 | 28800 | 99.16 | | CLBL | 15949 | 0 | | | | | CLBM | 12609 | 0 | | | | | LUT as Logic | 126527 | 0 | 0 | 230400 | 54.92 | | using O5 output only | 2094 | | | | | | using O6 output only | 93835 | | | | | | using O5 and O6 | 30598 | | | | | | LUT as Memory | 12138 | 0 | 0 | 101760 | 11.93 | | LUT as Distributed RAM | 1240 | 0 | | | | | using O5 output only | 0 | | | | | | using O6 output only | 1160 | | | | | | using O5 and O6 | 80 | | | | | | LUT as Shift Register | 10898 | 0 | | | | | using O5 output only | 0 | | | | | | using O6 output only | 7829 | | | | | | using O5 and O6 | 3069 | | | | | | CLB Registers | 260021 | 0 | 0 | 460800 | 56.43 | | Register driven from within the CLB | 108727 | | | | | | Register driven from outside the CLB | 151294 | | | | | | LUT in front of the register is unused | 82465 | | | | | | LUT in front of the register is used | 68829 | | | | | | Unique Control Sets | 8300 | | 0 | 57600 | 14.41 | +--------------------------------------------+--------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets. 3. BLOCKRAM ----------- +-------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------+------+-------+------------+-----------+-------+ | Block RAM Tile | 285 | 0 | 0 | 312 | 91.35 | | RAMB36/FIFO* | 270 | 0 | 0 | 312 | 86.54 | | RAMB36E2 only | 270 | | | | | | RAMB18 | 30 | 0 | 0 | 624 | 4.81 | | RAMB18E2 only | 30 | | | | | | URAM | 25 | 0 | 0 | 96 | 26.04 | +-------------------+------+-------+------------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2 4. ARITHMETIC ------------- +----------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------+------+-------+------------+-----------+-------+ | DSPs | 350 | 0 | 0 | 1728 | 20.25 | | DSP48E2 only | 350 | | | | | +----------------+------+-------+------------+-----------+-------+ 5. I/O ------ +------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------------+------+-------+------------+-----------+-------+ | Bonded IOB | 37 | 37 | 0 | 360 | 10.28 | | HPIOB_M | 9 | 9 | 0 | 144 | 6.25 | | INPUT | 4 | | | | | | OUTPUT | 3 | | | | | | BIDIR | 2 | | | | | | HPIOB_S | 10 | 10 | 0 | 144 | 6.94 | | INPUT | 4 | | | | | | OUTPUT | 6 | | | | | | BIDIR | 0 | | | | | | HDIOB_M | 9 | 9 | 0 | 24 | 37.50 | | INPUT | 1 | | | | | | OUTPUT | 3 | | | | | | BIDIR | 5 | | | | | | HDIOB_S | 9 | 9 | 0 | 24 | 37.50 | | INPUT | 3 | | | | | | OUTPUT | 1 | | | | | | BIDIR | 5 | | | | | | HPIOB_SNGL | 0 | 0 | 0 | 24 | 0.00 | | HPIOBDIFFINBUF | 0 | 0 | 0 | 192 | 0.00 | | HPIOBDIFFOUTBUF | 0 | 0 | 0 | 192 | 0.00 | | HDIOBDIFFINBUF | 0 | 0 | 0 | 48 | 0.00 | | BITSLICE_CONTROL | 0 | 0 | 0 | 64 | 0.00 | | BITSLICE_RX_TX | 0 | 0 | 0 | 2496 | 0.00 | | BITSLICE_TX | 0 | 0 | 0 | 64 | 0.00 | | RIU_OR | 0 | 0 | 0 | 32 | 0.00 | +------------------+------+-------+------------+-----------+-------+ 6. CLOCK -------- +----------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------+------+-------+------------+-----------+-------+ | GLOBAL CLOCK BUFFERs | 24 | 0 | 0 | 544 | 4.41 | | BUFGCE | 3 | 0 | 0 | 208 | 1.44 | | BUFGCE_DIV | 0 | 0 | 0 | 32 | 0.00 | | BUFG_GT | 20 | 0 | 0 | 144 | 13.89 | | BUFG_PS | 1 | 0 | 0 | 96 | 1.04 | | BUFGCTRL* | 0 | 0 | 0 | 64 | 0.00 | | PLL | 0 | 0 | 0 | 16 | 0.00 | | MMCM | 1 | 0 | 0 | 8 | 12.50 | +----------------------+------+-------+------------+-----------+-------+ * Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability. 7. ADVANCED ----------- +-----------------+------+-------+------------+-----------+--------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------+------+-------+------------+-----------+--------+ | GTHE4_CHANNEL | 10 | 10 | 0 | 20 | 50.00 | | GTHE4_COMMON | 3 | 0 | 0 | 5 | 60.00 | | OBUFDS_GTE4 | 0 | 0 | 0 | 10 | 0.00 | | OBUFDS_GTE4_ADV | 0 | 0 | 0 | 10 | 0.00 | | PCIE40E4 | 0 | 0 | 0 | 2 | 0.00 | | PS8 | 1 | 0 | 0 | 1 | 100.00 | | SYSMONE4 | 0 | 0 | 0 | 1 | 0.00 | | VCU | 1 | 0 | 0 | 1 | 100.00 | +-----------------+------+-------+------------+-----------+--------+ 8. CONFIGURATION ---------------- +-------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------+------+-------+------------+-----------+-------+ | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | DNA_PORTE2 | 0 | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | FRAME_ECCE4 | 0 | 0 | 0 | 1 | 0.00 | | ICAPE3 | 0 | 0 | 0 | 2 | 0.00 | | MASTER_JTAG | 0 | 0 | 0 | 1 | 0.00 | | STARTUPE3 | 0 | 0 | 0 | 1 | 0.00 | +-------------+------+-------+------------+-----------+-------+ 9. Primitives ------------- +---------------+--------+---------------------+ | Ref Name | Used | Functional Category | +---------------+--------+---------------------+ | FDRE | 242424 | Register | | LUT6 | 49205 | CLB | | LUT3 | 35758 | CLB | | LUT4 | 26087 | CLB | | LUT5 | 23655 | CLB | | LUT2 | 18076 | CLB | | FDCE | 12466 | Register | | SRL16E | 7989 | CLB | | SRLC32E | 5978 | CLB | | MUXF7 | 5558 | CLB | | FDSE | 4655 | Register | | LUT1 | 4344 | CLB | | CARRY8 | 2808 | CLB | | MUXF8 | 1503 | CLB | | RAMS64E | 1152 | CLB | | FDPE | 476 | Register | | DSP48E2 | 350 | Arithmetic | | RAMB36E2 | 270 | BLOCKRAM | | RAMD32 | 148 | CLB | | RAMB18E2 | 30 | BLOCKRAM | | URAM288 | 25 | BLOCKRAM | | INBUF | 24 | I/O | | IBUFCTRL | 24 | Others | | RAMS32 | 20 | CLB | | BUFG_GT_SYNC | 20 | Clock | | BUFG_GT | 20 | Clock | | OBUF | 13 | I/O | | OBUFT | 12 | I/O | | GTHE4_CHANNEL | 10 | Advanced | | IBUFDS_GTE4 | 3 | I/O | | GTHE4_COMMON | 3 | Advanced | | BUFGCE | 3 | Clock | | VCU | 1 | Advanced | | PS8 | 1 | Advanced | | MMCME4_ADV | 1 | Clock | | BUFG_PS | 1 | Clock | +---------------+--------+---------------------+ 10. Black Boxes --------------- +----------+------+ | Ref Name | Used | +----------+------+ 11. Instantiated Netlists ------------------------- +---------------------------------+------+ | Ref Name | Used | +---------------------------------+------+ | bd_baeb_v_vid_sdi_tx_bridge_0 | 1 | | bd_baeb_v_tc_0 | 1 | | bd_baeb_v_smpte_uhdsdi_tx_0 | 1 | | bd_baeb_v_axi4s_vid_out_0 | 1 | | bd_baeb_axi_crossbar_0 | 1 | | bd_b92b_v_vid_sdi_tx_bridge_0 | 1 | | bd_b92b_v_tc_0 | 1 | | bd_b92b_v_smpte_uhdsdi_tx_0 | 1 | | bd_b92b_v_axi4s_vid_out_0 | 1 | | bd_b92b_axi_crossbar_0 | 1 | | bd_b86b_v_vid_sdi_tx_bridge_0 | 1 | | bd_b86b_v_tc_0 | 1 | | bd_b86b_v_smpte_uhdsdi_tx_0 | 1 | | bd_b86b_v_axi4s_vid_out_0 | 1 | | bd_b86b_axi_crossbar_0 | 1 | | bd_ae07_vsc_0 | 1 | | bd_ae07_smartconnect_0_0 | 1 | | bd_ae07_rst_axis_0 | 1 | | bd_ae07_reset_sel_axis_0 | 1 | | bd_ae07_input_size_set_0 | 1 | | bd_ae07_hsc_0 | 1 | | bd_ae07_axis_register_slice_0_0 | 1 | | bd_ae07_axis_fifo_0 | 1 | | bd_aa93_v_vid_sdi_tx_bridge_0 | 1 | | bd_aa93_v_tc_0 | 1 | | bd_aa93_v_smpte_uhdsdi_tx_0 | 1 | | bd_aa93_v_axi4s_vid_out_0 | 1 | | bd_aa93_axi_crossbar_0 | 1 | | bd_aa47_vsc_0 | 1 | | bd_aa47_smartconnect_0_0 | 1 | | bd_aa47_rst_axis_0 | 1 | | bd_aa47_reset_sel_axis_0 | 1 | | bd_aa47_input_size_set_0 | 1 | | bd_aa47_hsc_0 | 1 | | bd_aa47_axis_register_slice_0_0 | 1 | | bd_aa47_axis_fifo_0 | 1 | | bd_a78b_v_vid_in_axi4s_0 | 1 | | bd_a78b_v_smpte_uhdsdi_rx_0 | 1 | | bd_a78b_v_sdi_rx_vid_bridge_0 | 1 | | bd_974a_v_vid_in_axi4s_0 | 1 | | bd_974a_v_smpte_uhdsdi_rx_0 | 1 | | bd_974a_v_sdi_rx_vid_bridge_0 | 1 | | bd_95ca_v_vid_in_axi4s_0 | 1 | | bd_95ca_v_smpte_uhdsdi_rx_0 | 1 | | bd_95ca_v_sdi_rx_vid_bridge_0 | 1 | | bd_948a_v_vid_in_axi4s_0 | 1 | | bd_948a_v_smpte_uhdsdi_rx_0 | 1 | | bd_948a_v_sdi_rx_vid_bridge_0 | 1 | | bd_90ca_v_vid_in_axi4s_0 | 1 | | bd_90ca_v_smpte_uhdsdi_rx_0 | 1 | | bd_90ca_v_sdi_rx_vid_bridge_0 | 1 | | bd_7a2a_v_vid_sdi_tx_bridge_0 | 1 | | bd_7a2a_v_tc_0 | 1 | | bd_7a2a_v_smpte_uhdsdi_tx_0 | 1 | | bd_7a2a_v_axi4s_vid_out_0 | 1 | | bd_7a2a_axi_crossbar_0 | 1 | | bd_79ea_v_vid_sdi_tx_bridge_0 | 1 | | bd_79ea_v_tc_0 | 1 | | bd_79ea_v_smpte_uhdsdi_tx_0 | 1 | | bd_79ea_v_axi4s_vid_out_0 | 1 | | bd_79ea_axi_crossbar_0 | 1 | | bd_78aa_v_vid_sdi_tx_bridge_0 | 1 | | bd_78aa_v_tc_0 | 1 | | bd_78aa_v_smpte_uhdsdi_tx_0 | 1 | | bd_78aa_v_axi4s_vid_out_0 | 1 | | bd_78aa_axi_crossbar_0 | 1 | | bd_6f86_vsc_0 | 1 | | bd_6f86_smartconnect_0_0 | 1 | | bd_6f86_rst_axis_0 | 1 | | bd_6f86_reset_sel_axis_0 | 1 | | bd_6f86_input_size_set_0 | 1 | | bd_6f86_hsc_0 | 1 | | bd_6f86_axis_register_slice_0_0 | 1 | | bd_6f86_axis_fifo_0 | 1 | | bd_6ec6_vsc_0 | 1 | | bd_6ec6_smartconnect_0_0 | 1 | | bd_6ec6_rst_axis_0 | 1 | | bd_6ec6_reset_sel_axis_0 | 1 | | bd_6ec6_input_size_set_0 | 1 | | bd_6ec6_hsc_0 | 1 | | bd_6ec6_axis_register_slice_0_0 | 1 | | bd_6ec6_axis_fifo_0 | 1 | | bd_6a52_v_vid_sdi_tx_bridge_0 | 1 | | bd_6a52_v_tc_0 | 1 | | bd_6a52_v_smpte_uhdsdi_tx_0 | 1 | | bd_6a52_v_axi4s_vid_out_0 | 1 | | bd_6a52_axi_crossbar_0 | 1 | | bd_674a_v_vid_in_axi4s_0 | 1 | | bd_674a_v_smpte_uhdsdi_rx_0 | 1 | | bd_674a_v_sdi_rx_vid_bridge_0 | 1 | | bd_578b_v_vid_in_axi4s_0 | 1 | | bd_578b_v_smpte_uhdsdi_rx_0 | 1 | | bd_578b_v_sdi_rx_vid_bridge_0 | 1 | | bd_544b_v_vid_in_axi4s_0 | 1 | | bd_544b_v_smpte_uhdsdi_rx_0 | 1 | | bd_544b_v_sdi_rx_vid_bridge_0 | 1 | | bd_500b_v_vid_in_axi4s_0 | 1 | | bd_500b_v_smpte_uhdsdi_rx_0 | 1 | | bd_500b_v_sdi_rx_vid_bridge_0 | 1 | | bd_060b_v_vid_in_axi4s_0 | 1 | | bd_060b_v_smpte_uhdsdi_rx_0 | 1 | | bd_060b_v_sdi_rx_vid_bridge_0 | 1 | | arm_zynq_ultra_ps_e_0_0 | 1 | | arm_xbar_9 | 1 | | arm_xbar_8 | 1 | | arm_xbar_7 | 1 | | arm_xbar_6 | 1 | | arm_xbar_35 | 1 | | arm_xbar_34 | 1 | | arm_xbar_33 | 1 | | arm_xbar_32 | 1 | | arm_xbar_28 | 1 | | arm_xbar_27 | 1 | | arm_xbar_25 | 1 | | arm_xbar_16 | 1 | | arm_xbar_15 | 1 | | arm_xbar_14 | 1 | | arm_xbar_1 | 1 | | arm_xbar_0 | 1 | | arm_vcu_0_0 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_15 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_14 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_13 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_12 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_11 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_10 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_1 | 1 | | arm_v_smpte_uhdsdi_tx_ss_0_0 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_30 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_29 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_28 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_27 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_26 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_25 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_23 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_22 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_13 | 1 | | arm_v_smpte_uhdsdi_rx_ss_0_12 | 1 | | arm_v_proc_ss_0_18 | 1 | | arm_v_proc_ss_0_17 | 1 | | arm_v_proc_ss_0_16 | 1 | | arm_v_proc_ss_0_15 | 1 | | arm_v_mix_0_1 | 1 | | arm_v_frmbuf_wr_0_30 | 1 | | arm_v_frmbuf_wr_0_29 | 1 | | arm_v_frmbuf_wr_0_28 | 1 | | arm_v_frmbuf_wr_0_27 | 1 | | arm_v_frmbuf_wr_0_26 | 1 | | arm_v_frmbuf_wr_0_25 | 1 | | arm_v_frmbuf_wr_0_23 | 1 | | arm_v_frmbuf_wr_0_22 | 1 | | arm_v_frmbuf_wr_0_13 | 1 | | arm_v_frmbuf_wr_0_12 | 1 | | arm_v_frmbuf_rd_0_15 | 1 | | arm_v_frmbuf_rd_0_14 | 1 | | arm_v_frmbuf_rd_0_13 | 1 | | arm_v_frmbuf_rd_0_12 | 1 | | arm_v_frmbuf_rd_0_11 | 1 | | arm_v_frmbuf_rd_0_10 | 1 | | arm_v_frmbuf_rd_0_1 | 1 | | arm_v_frmbuf_rd_0_0 | 1 | | arm_util_ds_buf_0_6 | 1 | | arm_util_ds_buf_0_4 | 1 | | arm_util_ds_buf_0_0 | 1 | | arm_uhdsdi_gt_0_6 | 1 | | arm_uhdsdi_gt_0_4 | 1 | | arm_uhdsdi_gt_0_0 | 1 | | arm_sdi_anc_tx_0_9 | 1 | | arm_sdi_anc_tx_0_8 | 1 | | arm_sdi_anc_tx_0_7 | 1 | | arm_sdi_anc_tx_0_6 | 1 | | arm_sdi_anc_tx_0_5 | 1 | | arm_sdi_anc_tx_0_4 | 1 | | arm_sdi_anc_tx_0_1 | 1 | | arm_sdi_anc_tx_0_0 | 1 | | arm_proc_sys_reset_0_1 | 1 | | arm_proc_sys_reset_0_0 | 1 | | arm_compact_gt_ctrl_0_0 | 1 | | arm_clk_wiz_0_0 | 1 | | arm_axi_intc_0_5 | 1 | | arm_axi_intc_0_3 | 1 | | arm_axi_intc_0_2 | 1 | | arm_axi_gpio_1_0 | 1 | | arm_axi_gpio_0_1 | 1 | | arm_axi_gpio_0_0 | 1 | | arm_auto_us_0 | 1 | | arm_auto_pc_1 | 1 | | arm_auto_pc_0 | 1 | | arm_auto_ds_1 | 1 | | arm_auto_ds_0 | 1 | +---------------------------------+------+